Technical Specifications

FPGA

Xilinx Spartan-6 LX150T-4, part nr. XC6SLX150T-4FGG676C. The device is capable of 23,038 slices, i.e. 92,152 6-input LUTs and 184,304 flip-flops. It features 180 DSP slices, 4.8 MBit of BRAM memory and up to 1.3 Mbit distributed memory.

We use the fastest speed grade available (-4), which allows to fully utilize the DDR2-DRAM at 400 MHz (800 Mbps/pin effective) as well as easily achieve high-speed internal logic -- our first large hardware project has multiple parts working at 160 MHz, having reached a >75% logic utilzation. We supply a 1.23V core voltage for the extended MCB operation at 400 MHz.

SRAM Memories

3 Cypress pipelined NoBL SRAMs, part nr. CY7C1354CV25-166BZC. Each memory has a capacity of 9 MBits, organized as 256K x 36 words. This provides a nominal 1 MB capacity with parity protection. The NoBL architecture is equivalent to zero-bus turnaround one (ZBT). The maximum frequency of operation is 166 MHz, resulting in a raw throughput of 5.3 Gbps per device.

All clocking, address, control and data pins are fully independent among the 3 devices. Each SRAM is clocked by a different FPGA output pin; each such PCB track also provides a matched-length feedback clock input, so that the FPGA deskewing logic can compensate for in-FPGA routing delays as well as PCB and temperature delays.

DRAM Memory

Micron DDR2 SDRAM, part nr. MT47H64M16HR-25E L:H. The device has a 1 Gbit capacity (128 MBytes), organized as 8 banks of 8M x 16. The operating frequency is 400 MHz DDR, which offers a peak bandwidth of 12.8 Gbps.

GTP Serial Links

The Spartan-6 LX150T has 8 high-speed serial link ports (called GTP, for Gigabit Transceiver Port) and we use all of them in Formic. Full specifications about the GTP ports can be found in the Xilinx User Guide 386. The FPGA GTP banks are clocked by dedicated external oscillators to minimize jiter. These are set to 150 MHz, so the links are tied to a raw 3.0 Gbps operation.

Each GTP port is connected to a standard SATA connector. A SATA connector offers a full bidirectional link capability and is the equivalent of 4 SMA/SMB cables (TX+, TX-, RX+, RX-). Half of the connectors are using the Host pinout and the other half the Device pinout. This allows board-to-board connections to be done using standard straight SATA cables. Host-to-host and device-to-device connections are still possible, using cross SATA cables.

Configuration PROM

Xilinx 32 Mbit PROM, part nr. XCF32PFSG48C (described in the Xilinx User Guide 161). The PROM holds up to 32 Mbits of configuration data and supports compression. The full configuration of the LX150T device is higher than that (36 Mbits), but compressing 36 Mbits to 32 Mbits will be adequate for most designs -- we have not seen any configuration file that we could not compress so far. The FPGA/PROM connectivity is set to Slave Serial mode to support the compression. The PROM is programmed through the JTAG chain.

Clocking Sources

3 Silicon Devices Si500D devices (product family). We use 2 devices set at 150 MHz (part nr. 500DSAC-ACF-ND) to individually clock the top and bottom FPGA GTP banks. We use a 3rd device set at 200 MHz (part nr. 500DLAC-ACF-ND) to provide a 200 MHz FPGA user clock input. All clocking sources are of very high quality (< 1.5 ps jitter) and are provided in differential pairs. They are monolithic and do not need by external crystal resonators.

PCB Characteristics

The Printed Circuit Board consists of 10 layers. The stack-up is split for the GTP link areas and the purely digital areas as follows:

Layer Digital stack-up GTP stack-up
1 Top signal Top signal
2 Power Ground
3 Ground Signal
4 Signal Ground
5 Signal Signal
6 Ground Ground
7 Signal Power
8 Signal Ground
9 Ground unused for GTP
10 Bottom signal / power unused for GTP

The minimum trace width is 5 mils (0.127 mm) and the minimum drilled holes are 0.3 mm. Most BGA pitches are 1.0 mm, except for the DRAM which has 0.8 mm. All DDR2, SRAM and GTP tracks are length-matched according to the proper rules to ensure signal quality. All DDR2 and SRAM signals are routed only within internal signal layers. All GTP differential pairs are referenecd to ground planes.

Power Supplies

The board gets a single power supply of 12 V. There are two terminal blocks connected in parallel, one in the left side and one on the right side of the board. Boards can be chained to one another in this fashion, to minimize power cables in larger systems.

The on-board power grid is created by 7 Texas Instruments regulators, connected as follows (indentation indicates regulator chaining):

Voltage Max Current Regulator Usage
12 V -- -- Power source
├─ 3.3 V 0.1 A LM317LCPK RS-232, bias to 1.2 V regulators
├─ 2.5 V 6.0 A PTH08T231WAD SRAMs
│   └─ 0.9 V 1.0 A TPS51200DRCR DRAM termination
├─ 1.8 V 6.0 A PTH08T231WAD DRAM
│   ├─ 1.2 V 1.5 A TPS74201RGW Upper GTP banks
│   └─ 1.2 V 1.5 A TPS74201RGW Lower GTP banks
└─ 1.23 V 10.0 A PTH08T241WAD FPGA core voltage

Digital part regulators (DRAM/SRAM/FPGA core) are switching to support enough load and have ultra-fast response times. Top and bottom GTP banks regulators are separated; both are linear to further minimize power supply noise. For the DDR2 address/control pins termination, a special sink/source tracking regulator halves the 1.8 V to 0.9 V. Abundant decoupling is provided for all regulators with ceramic capacitors to improve response times even further.

JTAG Chain

The board JTAG chain consists of the FPGA, the configuration PROM and the 3 SRAMs. A first slide switch selects if the SRAMs are part of the chain or if they are bypassed. A second slide switch selects whether the chain is terminated on this board, or if it is buffered and cascaded to the next board. The chain is entered from the left JTAG connector and (if not terminated) continues through the right one. The connectors are of standard pitch (2.54 mm) to accommodate common, low-costribbon cable connections.

DIPs, LEDs, Reset

There are 12 DIP switches connected to input FPGA pins. There are also 12 small, bright LEDs (Kingbright, part nr. APHHS1005SECK) to output FPGA pins in a 2.5 V bank. The LEDs can be driven as-is for relatively bright lights, or they can be pulse-modulated to achieve dimmer modes. A large, panic-like reset button is debounced and connected to an input FPGA pin.

Other Ports

A standard RS-232 serial port with a 3.3 V line driver (Analog Devices part nr. ADM3101E) is provided for serial communication up to 460 Kbps. Two generic FPGA pins are connected to a 3-pin 2.54 mm standard connector (where the 3rd pin is grounded), which can be used for simple management serial protocols, such as I2C.

Power Consumption

In room temperature, tested boards consume approximately 0.18 A at the 12 V input (2.16 W) when the FPGA is deprogrammed. Our self-test program, which utlizies heavily all SRAMs, DRAM and GTP links, but only with a 10% FPGA utilization, consumes around 0.72 A (8.64 W). Our initial hardware design, which uses 2 of the 3 SRAMs, the DRAM and a few links at a time, but with a >75% FPGA utilization and internal speeds of up to 160 MHz, averages 0.56 A (6.72 W).

For all cases, we found that a passive cooler for the FPGA is adequate, especially when combined with a gentle system-wide airflow of larger fans which cover multiple boards simultaneously. Completely fanless operation shoud still be fine for normal usage scenarios.